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CR16MAS9 - Family of 16-bit CAN-enabled CompactRISC Microcontrollers

Download the CR16MAS9 datasheet PDF. This datasheet also covers the CR1 variant, as both devices belong to the same family of 16-bit can-enabled compactrisc microcontrollers family and are provided as variant models within a single manufacturer datasheet.

Description

plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost.

The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.

Features

  • and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com- Block Diagram Fast Clk Slow Clk.
  • CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit Core Bus Peripheral Bus Controller 64k-Byte Flash Program Memory 3k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Periphe.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CR1-6MA.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers January 2002 CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers 1.0 General Description plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers.
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